Timing recovery is an important function of many Ethernet systems. Because data is typically transmitted from one device to another in an asynchronous manner (i.e., without an accompanying clock signal), the receiving (RX) device generates an internal clock signal that is both frequency-aligned and phase-aligned with the received data signal. For example, if data is transmitted by a transmitting (TX) device using a 100 MHz clock signal, the RX device would ideally use a local 100 MHz clock to sample the received data signal. However, the RX device may have to adjust the frequency of the local clock signal to correct for drift in its oscillators and/or transmission paths. Further, the phase of the local clock signal may be adjusted so that it is aligned with the received data signal such that the RX device samples each data symbol at its peak (e.g., to reduce the effects of intersymbol interference).
Higher-frequency data rates correlate with shorter symbol (peak) durations, thus providing a smaller window within which a RX device can accurately sample a received data signal. Intersymbol interference (ISI) is also more pronounced at higher frequencies. Accordingly, as data rates increase, so too does the need for precise and accurate timing recovery circuitry.